--verified n tested-----------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:57:57 01/16/2011 
-- Design Name: 
-- Module Name:    RAM - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.LCSE.all;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RAM is
	Port(
			Reset : in std_logic;
			Clk : in std_logic;								
			Databus : inout std_logic_vector(7 downto 0); ---data bus
			Address : in std_logic_vector(7 downto 0);  --address bus
			CS : in std_logic;			--chip select
			write_en : in std_logic;   --write enable
			OE : in std_logic;			--read enable
			Switches : out std_logic_vector(7 downto 0); ---switch state
			Temp_L : out std_logic_vector(6 downto 0);		---7 segment display lowest temperature value of thermostat
			Temp_H : out std_logic_vector(6 downto 0)		---7 segment display highest temperature value of thermostat
		 );

end RAM;

architecture Behav of RAM is
--------GPIO RAM----------------------------------------------------------------------------------- 
SUBTYPE array8_ram IS std_logic_vector (7 downto 0);
TYPE gpio_r IS array (0 to 191) of array8_ram;
signal gpio_ram: gpio_r ; ---general purpose RAM (0xFF-0x3F)= 192 bytes

signal address_gpio:integer;
--------Specific Registers of RAM------------------------------------------------------------------
subtype register_ram is std_logic_vector (7 downto 0);
TYPE register_ram_s IS array (0 to 63)of register_ram;
signal reg_ram_s  :register_ram_s;

------reserved 0x2A to 0x30; 0x18 to 0x1f; 0x06 to 0x0f
  
signal temp_led: std_logic_vector(7 downto 0);

begin

address_gpio <= (Conv_integer(Address)-64);
---------------------------------------------------------
ram: process(Clk,Reset,Write_en,OE,Address,reg_ram_s)

	begin
		if (Reset='0') then---all the buffers are reset
			reg_ram_s(conv_integer(DMA_RX_BUFFER_MSB)) <=(others => '0');---RX buffer for DMA --0x00 to 0x02
			reg_ram_s(conv_integer(DMA_RX_BUFFER_MID)) <=(others => '0');--0x01
			reg_ram_s(conv_integer(DMA_RX_BUFFER_LSB)) <=(others => '0');--0x02 

			reg_ram_s(conv_integer(NEW_INST))        	 <=(others => '0');--0x03--flag indicates the arrival of new serial line

			reg_ram_s(conv_integer(DMA_TX_BUFFER_MSB)) <=(others => '0');--0x04--TX buffer for DMA-- 0x04 to 0x05 
			reg_ram_s(conv_integer(DMA_TX_BUFFER_LSB)) <=(others => '0');--0x05
				

			reg_ram_s(conv_integer(SWITCH_BASE))		 <=(others => '0');---0x10 to 0x17
			reg_ram_s(conv_integer(LEVER_BASE))			 <=(others => '0');--0x20 to 0x29
			reg_ram_s(conv_integer(T_STAT))				 <=(others => '0'); ---0x31 
	
			Databus<=(others =>'Z');
					
		elsif (Clk' event and Clk ='1') then
			if (Address< X"40")then ---write to the special registers
				
				if ((write_en = '1') and (OE ='0')) then--write
					------load value from data bus to the registers 
					case Address is
					 when  DMA_RX_BUFFER_MSB =>reg_ram_s(0) <= Databus;
					 when  DMA_RX_BUFFER_MID =>reg_ram_s(1) <= Databus;
					 when  DMA_RX_BUFFER_LSB =>reg_ram_s(2) <= Databus;
					 when  NEW_INST 			 =>reg_ram_s(3) <= Databus;
					 when  DMA_TX_BUFFER_MSB =>reg_ram_s(4) <= Databus;
					 when  DMA_TX_BUFFER_LSB =>reg_ram_s(5) <= Databus;
					 
					 when  SWITCH_BASE		 =>reg_ram_s(16) <= Databus;
					 when  SWITCH_BASE+1		 =>reg_ram_s(17) <= Databus;
					 when  SWITCH_BASE+2		 =>reg_ram_s(18) <= Databus;
					 when  SWITCH_BASE+3		 =>reg_ram_s(19) <= Databus;
					 when  SWITCH_BASE+4		 =>reg_ram_s(20) <= Databus;
					 when  SWITCH_BASE+5		 =>reg_ram_s(21) <= Databus;
					 when  SWITCH_BASE+6     =>reg_ram_s(22) <= Databus;
					 when  SWITCH_BASE+7		 =>reg_ram_s(23) <= Databus;
					 
					 when  LEVER_BASE			 =>reg_ram_s(32) <= Databus;
					 when  LEVER_BASE+1		 =>reg_ram_s(33) <= Databus;
					 when  LEVER_BASE+2		 =>reg_ram_s(34) <= Databus;
					 when  LEVER_BASE+3		 =>reg_ram_s(35) <= Databus;
					 when  LEVER_BASE+4		 =>reg_ram_s(36) <= Databus;
					 when  LEVER_BASE+5		 =>reg_ram_s(37) <= Databus;
					 when  LEVER_BASE+6		 =>reg_ram_s(38) <= Databus;
					 when  LEVER_BASE+7		 =>reg_ram_s(39) <= Databus;
					 when  LEVER_BASE+8		 =>reg_ram_s(40) <= Databus;
					 when  LEVER_BASE+9		 =>reg_ram_s(41) <= Databus;
					 
					 when  T_STAT				 =>reg_ram_s(49) <= Databus;
					 when others             =>reg_ram_s<=(others => "00000000");
					end case;

		
			--read value from the data bus to the registers 
		
				elsif (OE = '1' and Write_en ='0') then--read
					case Address is
					 when  DMA_RX_BUFFER_MSB => Databus<= reg_ram_s(0) ;
					 when  DMA_RX_BUFFER_MID => Databus<= reg_ram_s(1) ;
					 when  DMA_RX_BUFFER_LSB => Databus<= reg_ram_s(2) ;
					 when  NEW_INST 			 => Databus<= reg_ram_s(3) ;
					 when  DMA_TX_BUFFER_MSB => Databus<= reg_ram_s(4) ;
					 when  DMA_TX_BUFFER_LSB => Databus<= reg_ram_s(5) ;
					 
					 when  SWITCH_BASE		 => Databus<= reg_ram_s(16) ;
					 when  SWITCH_BASE+1		 => Databus<= reg_ram_s(17) ;
					 when  SWITCH_BASE+2		 => Databus<= reg_ram_s(18) ;
					 when  SWITCH_BASE+3		 => Databus<= reg_ram_s(19) ;
					 when  SWITCH_BASE+4		 => Databus<= reg_ram_s(20) ;
					 when  SWITCH_BASE+5		 => Databus<= reg_ram_s(21) ;
					 when  SWITCH_BASE+6     => Databus<= reg_ram_s(22) ;
					 when  SWITCH_BASE+7		 => Databus<= reg_ram_s(23) ;
					 
					 when  LEVER_BASE			 => Databus<= reg_ram_s(32) ;
					 when  LEVER_BASE+1		 => Databus<= reg_ram_s(33) ;
					 when  LEVER_BASE+2		 => Databus<= reg_ram_s(34) ;
					 when  LEVER_BASE+3		 => Databus<= reg_ram_s(35) ;
					 when  LEVER_BASE+4		 => Databus<= reg_ram_s(36) ;
					 when  LEVER_BASE+5		 => Databus<= reg_ram_s(37) ;
					 when  LEVER_BASE+6		 => Databus<= reg_ram_s(38) ;
					 when  LEVER_BASE+7		 => Databus<= reg_ram_s(39) ;
					 when  LEVER_BASE+8		 => Databus<= reg_ram_s(40) ;
					 when  LEVER_BASE+9		 => Databus<= reg_ram_s(41) ;
					 
					 when  T_STAT				 =>Databus<= reg_ram_s(49)  ;
					 when others 				 =>Databus<= (others => 'Z');
					end case;
				else
					Databus <= (others => 'Z');
				end if;
			
			elsif (Address > X"40") then -------address of gpio register location is from 40H
				if((Write_en = '1') and (OE ='0'))then--write to the gpio 
					gpio_ram(address_gpio) <= Databus;--data on the databus is written in the general purpose RAM
				elsif((Write_en = '0') and (OE ='1')) then -- read operation from gpio
					Databus<=gpio_ram(address_gpio);
				else
					Databus<= (others=>'Z');
				end if;
			end if;--address
		else
			Databus <= (others => 'Z');
		end if;--clking
	end process ram;

-----switches display-------------------------------

switches(0) <= reg_ram_s(16)(0); 
switches(1) <= reg_ram_s(17)(0); 
switches(2) <= reg_ram_s(18)(0); 
switches(3) <= reg_ram_s(19)(0); 
switches(4) <= reg_ram_s(20)(0); 
switches(5) <= reg_ram_s(21)(0); 
switches(6) <= reg_ram_s(22)(0); 
switches(7) <= reg_ram_s(23)(0); 

-----glow the LED for 7 segment display--------------------------
with temp_led(7 downto 4) select
Temp_H <=
    "0000110" when "0001",  -- 1
    "1011011" when "0010",  -- 2
    "1001111" when "0011",  -- 3
    "1100110" when "0100",  -- 4
    "1101101" when "0101",  -- 5
    "1111101" when "0110",  -- 6
    "0000111" when "0111",  -- 7
    "1111111" when "1000",  -- 8
    "1101111" when "1001",  -- 9
    "1110111" when "1010",  -- A
    "1111100" when "1011",  -- B
    "0111001" when "1100",  -- C
    "1011110" when "1101",  -- D
    "1111001" when "1110",  -- E
    "1110001" when "1111",  -- F
    "0111111" when others;  -- 0

with temp_led(3 downto 0) select 
Temp_L <=
    "0000110" when "0001",  -- 1
    "1011011" when "0010",  -- 2
    "1001111" when "0011",  -- 3
    "1100110" when "0100",  -- 4
    "1101101" when "0101",  -- 5
    "1111101" when "0110",  -- 6
    "0000111" when "0111",  -- 7
    "1111111" when "1000",  -- 8
    "1101111" when "1001",  -- 9
    "1110111" when "1010",  -- A
    "1111100" when "1011",  -- B
    "0111001" when "1100",  -- C
    "1011110" when "1101",  -- D
    "1111001" when "1110",  -- E
    "1110001" when "1111",  -- F
    "0111111" when others;  -- 0

end Behav;

----					if Address = DMA_RX_BUFFER_MSB then
----						reg_ram_s(0) <= Databus;
----					elsif Address = DMA_RX_BUFFER_MID then
----						reg_ram_s(1) <= Databus;
----					elsif Address = DMA_RX_BUFFER_LSB then
----						reg_ram_s(2) <= Databus;
----					elsif Address = NEW_INST then
----						reg_ram_s(3) <= Databus;
----					elsif Address = DMA_TX_BUFFER_MSB then
----						reg_ram_s(4) <= Databus;
----					elsif Address = DMA_TX_BUFFER_LSB then
--						reg_ram_s(5) <= Databus;
--					elsif Address = SWITCH_BASE then--x10
--						reg_ram_s(16) <= Databus;
--					elsif Address = SWITCH_BASE+1 then
--						reg_ram_s(17) <= Databus;
--					elsif Address = SWITCH_BASE+2 then
--						reg_ram_s(18) <= Databus;
--					elsif Address = SWITCH_BASE+3 then
--						reg_ram_s(19) <= Databus;
--					elsif Address = SWITCH_BASE+4 then
--						reg_ram_s(20) <= Databus;
--					elsif Address = SWITCH_BASE+5 then
--						reg_ram_s(21) <= Databus;
--					elsif Address = SWITCH_BASE+6 then
--						reg_ram_s(22) <= Databus;
--					elsif Address = SWITCH_BASE+7 then--x17
--						reg_ram_s(23) <= Databus;
--					elsif Address = LEVER_BASE then--x20
--						reg_ram_s(32) <= Databus;
--					elsif Address = LEVER_BASE+1 then
--						reg_ram_s(33) <= Databus;
--					elsif Address = LEVER_BASE+2 then
--						reg_ram_s(34) <= Databus;
--					elsif Address = LEVER_BASE+3 then
--						reg_ram_s(35) <= Databus;
--					elsif Address = LEVER_BASE+4 then
--						reg_ram_s(36) <= Databus;
--				 	elsif Address = LEVER_BASE+5 then
--						reg_ram_s(37) <= Databus;
--				  	elsif Address = LEVER_BASE+6 then
--						reg_ram_s(38) <= Databus;
--				  	elsif Address = LEVER_BASE+7 then
--						reg_ram_s(39) <= Databus;
--				 	elsif Address = LEVER_BASE+8 then
--						reg_ram_s(40) <= Databus;
--			    	elsif Address = LEVER_BASE+9 then--29
--						reg_ram_s(41) <= Databus;
--					elsif Address = CAL_OP then--x30
--						reg_ram_s(49) <= Databus;
--					elsif Address = T_STAT then--31
--						reg_ram_s(50) <= Databus;
--					end if;


					
--					if Address = DMA_RX_BUFFER_MSB then
--						Databus <= reg_ram_s(0);
--					elsif Address = DMA_RX_BUFFER_MID then
--						Databus <= reg_ram_s(1);
--					elsif Address = DMA_RX_BUFFER_LSB then
--						Databus <= reg_ram_s(2);
--					elsif Address = NEW_INST then
--						Databus <= reg_ram_s(3);
--					elsif Address = DMA_TX_BUFFER_MSB then
--						Databus <= reg_ram_s(4);
--					elsif Address = DMA_TX_BUFFER_LSB then
--						Databus <= reg_ram_s(5);
--					elsif Address = SWITCH_BASE then--x10
--						Databus <= reg_ram_s(16);
--					elsif Address = SWITCH_BASE+1 then
--						Databus <= reg_ram_s(17);
--					elsif Address = SWITCH_BASE+2 then
--						Databus <= reg_ram_s(18);
--					elsif Address = SWITCH_BASE+3 then
--						Databus <= reg_ram_s(19);
--					elsif Address = SWITCH_BASE+4 then
--						Databus <= reg_ram_s(20);
--					elsif Address = SWITCH_BASE+5 then
--						Databus <= reg_ram_s(21);
--					elsif Address = SWITCH_BASE+6 then
--						Databus <= reg_ram_s(22);
--					elsif Address = SWITCH_BASE+7 then--x17
--						Databus <= reg_ram_s(23);
--					elsif Address = LEVER_BASE then--x20
--						Databus <= reg_ram_s(32);
--					elsif Address = LEVER_BASE+1 then
--						Databus <= reg_ram_s(33);
--					elsif Address = LEVER_BASE+2 then
--						Databus <= reg_ram_s(34);
--					elsif Address = LEVER_BASE+3 then
--						Databus <= reg_ram_s(35);
--					elsif Address = LEVER_BASE+4 then
--						Databus <= reg_ram_s(36);
--				 	elsif Address = LEVER_BASE+5 then
--						Databus <= reg_ram_s(37);
--				  	elsif Address = LEVER_BASE+6 then
--						Databus <= reg_ram_s(38);
--				  	elsif Address = LEVER_BASE+7 then
--						Databus <= reg_ram_s(39);
--				 	elsif Address = LEVER_BASE+8 then
--						Databus <= reg_ram_s(40);
--					elsif Address = LEVER_BASE+9 then--x29
--						Databus <= reg_ram_s(41);
--					elsif Address = CAL_OP then--x31
--						Databus <= reg_ram_s(49);
--					elsif Address = T_STAT then--x32
--						Databus <= reg_ram_s(50);






























----verified n tested-----------------------------------------------------------------------
---- Company: 
---- Engineer: 
---- 
---- Create Date:    14:57:57 01/16/2011 
---- Design Name: 
---- Module Name:    RAM - Behavioral 
---- Project Name: 
---- Target Devices: 
---- Tool versions: 
---- Description: 
----
---- Dependencies: 
----
---- Revision: 
---- Revision 0.01 - File Created
---- Additional Comments: 
----
------------------------------------------------------------------------------------
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--USE work.LCSE.all;
--
--
------ Uncomment the following library declaration if instantiating
------ any Xilinx primitives in this code.
----library UNISIM;
----use UNISIM.VComponents.all;
--
--entity RAM is
--	Port(
--			Reset : in std_logic;
--			Clk : in std_logic;								
--			Databus : inout std_logic_vector( 7 downto 0); ---data bus
--			Address : in std_logic_vector(7 downto 0);  --address bus
--			CS : in std_logic;			--chip select
--			write_en : in std_logic;   --write enable
--			OE : in std_logic;			--read enable
--			Switches : out std_logic_vector(7 downto 0); ---switch state
--			Temp_L : out std_logic_vector(6 downto 0);		---7 segment display lowest temperature value of thermostat
--			Temp_H : out std_logic_vector(6 downto 0)		---7 segment display highest temperature value of thermostat
--		 );
--
--end RAM;
--
--architecture Behav of RAM is
----------GPIO RAM----------------------------------------------------------------------------------- 
--SUBTYPE array8_ram IS std_logic_vector (7 downto 0);
--TYPE gpio_r IS array (0 to 191) of array8_ram;
--signal gpio_ram: gpio_r ; ---general purpose RAM (0xFF-0x3F)= 192 bytes
--
--signal address_gpio:integer;
----------Specific Registers of RAM------------------------------------------------------------------
--subtype register_ram is std_logic_vector (7 downto 0);
--TYPE register_ram_s IS array (0 to 63)of register_ram;
--signal reg_ram_s  :register_ram_s;
--
--------reserved 0x2A to 0x30; 0x18 to 0x1f; 0x06 to 0x0f
--  
--signal temp_led: std_logic_vector(7 downto 0);
--
--begin
--
--address_gpio <= (Conv_integer(Address)-64);
-----------------------------------------------------------
--write_ram : process (Clk, write_en,OE )  -- no reset
--
--begin
--  if (Clk' event and Clk = '1') then
--	 if ((write_en = '1') and (OE ='0'))then--write to the gpio
--     	if (Address > X"40") then -------address of gpio register location is from 40H
--			gpio_ram(address_gpio) <= Databus;--data on the databus is written in the general purpose RAM
--		elsif ((write_en = '0') and (OE ='0')) then -- read operation from gpio
--			Databus<=gpio_ram(address_gpio);
--		else
--			Databus<= (others=>'Z');
--		end if;
--	end if;
--  end if;
--  
--
--end process write_ram;
---------------------------------------------------------
--ram: process(Clk,Reset,write_en,OE,Address)
--
--	begin
--
--		if (Reset='0') then---all the buffers are reset
--				reg_ram_s(conv_integer(DMA_RX_BUFFER_MSB)) <=(others => '0');---RX buffer for DMA --0x00 to 0x02
--				reg_ram_s(conv_integer(	DMA_RX_BUFFER_MID)) <=(others => '0');--0x01
--				reg_ram_s(conv_integer(DMA_RX_BUFFER_LSB)) <=(others => '0');--0x02 
--
--				reg_ram_s(conv_integer(NEW_INST))        	<=(others => '0');--0x03--flag indicates the arrival of new serial line
--
--				reg_ram_s(conv_integer(DMA_TX_BUFFER_MSB)) <=(others => '0');--0x04--TX buffer for DMA-- 0x04 to 0x05 
--				reg_ram_s(conv_integer(DMA_TX_BUFFER_LSB)) <=(others => '0');--0x05
--				
--
--				reg_ram_s(conv_integer(SWITCH_BASE))			<=(others => '0');---0x10 to 0x17
--				reg_ram_s(conv_integer(LEVER_BASE))				<=(others => '0');--0x20 to 0x29
--				reg_ram_s(conv_integer(T_STAT))				<=(others => '0'); ---0x31 and 0x32
--	
--			   Databus<=(others =>'Z');
--
--		elsif (Clk' event and Clk='1') then
--			
--			if (Address< X"40")then ---write to the special registers
--				if ((write_en = '1') and (OE ='0')) then
--					------load value from data bus to the registers 
--					if Address = DMA_RX_BUFFER_MSB then
--						reg_ram_s(0) <= Databus;
--					elsif Address = DMA_RX_BUFFER_MID then
--						reg_ram_s(1) <= Databus;
--					elsif Address = DMA_RX_BUFFER_LSB then
--						reg_ram_s(2) <= Databus;
--					elsif Address = NEW_INST then
--						reg_ram_s(3) <= Databus;
--					elsif Address = DMA_TX_BUFFER_MSB then
--						reg_ram_s(4) <= Databus;
--					elsif Address = DMA_TX_BUFFER_LSB then
--						reg_ram_s(5) <= Databus;
--					elsif Address = SWITCH_BASE then--x10
--						reg_ram_s(16) <= Databus;
--					elsif Address = SWITCH_BASE+1 then
--						reg_ram_s(17) <= Databus;
--					elsif Address = SWITCH_BASE+2 then
--						reg_ram_s(18) <= Databus;
--					elsif Address = SWITCH_BASE+3 then
--						reg_ram_s(19) <= Databus;
--					elsif Address = SWITCH_BASE+4 then
--						reg_ram_s(20) <= Databus;
--					elsif Address = SWITCH_BASE+5 then
--						reg_ram_s(21) <= Databus;
--					elsif Address = SWITCH_BASE+6 then
--						reg_ram_s(22) <= Databus;
--					elsif Address = SWITCH_BASE+7 then--x17
--						reg_ram_s(23) <= Databus;
--					elsif Address = LEVER_BASE then--x20
--						reg_ram_s(32) <= Databus;
--					elsif Address = LEVER_BASE+1 then
--						reg_ram_s(33) <= Databus;
--					elsif Address = LEVER_BASE+2 then
--						reg_ram_s(34) <= Databus;
--					elsif Address = LEVER_BASE+3 then
--						reg_ram_s(35) <= Databus;
--					elsif Address = LEVER_BASE+4 then
--						reg_ram_s(36) <= Databus;
--				 	elsif Address = LEVER_BASE+5 then
--						reg_ram_s(37) <= Databus;
--				  	elsif Address = LEVER_BASE+6 then
--						reg_ram_s(38) <= Databus;
--				  	elsif Address = LEVER_BASE+7 then
--						reg_ram_s(39) <= Databus;
--				 	elsif Address = LEVER_BASE+8 then
--						reg_ram_s(40) <= Databus;
--			    	elsif Address = LEVER_BASE+9 then--29
--						reg_ram_s(41) <= Databus;
--					elsif Address = CAL_OP then--x30
--						reg_ram_s(49) <= Databus;
--					elsif Address = T_STAT then--31
--						reg_ram_s(50) <= Databus;
--					end if;
--		
--			--read value from the data bus to the registers 
--		
--			elsif (OE = '1' and Write_en ='0') then
--					if Address = DMA_RX_BUFFER_MSB then
--						Databus <= reg_ram_s(0);
--					elsif Address = DMA_RX_BUFFER_MID then
--						Databus <= reg_ram_s(1);
--					elsif Address = DMA_RX_BUFFER_LSB then
--						Databus <= reg_ram_s(2);
--					elsif Address = NEW_INST then
--						Databus <= reg_ram_s(3);
--					elsif Address = DMA_TX_BUFFER_MSB then
--						Databus <= reg_ram_s(4);
--					elsif Address = DMA_TX_BUFFER_LSB then
--						Databus <= reg_ram_s(5);
--					elsif Address = SWITCH_BASE then--x10
--						Databus <= reg_ram_s(16);
--					elsif Address = SWITCH_BASE+1 then
--						Databus <= reg_ram_s(17);
--					elsif Address = SWITCH_BASE+2 then
--						Databus <= reg_ram_s(18);
--					elsif Address = SWITCH_BASE+3 then
--						Databus <= reg_ram_s(19);
--					elsif Address = SWITCH_BASE+4 then
--						Databus <= reg_ram_s(20);
--					elsif Address = SWITCH_BASE+5 then
--						Databus <= reg_ram_s(21);
--					elsif Address = SWITCH_BASE+6 then
--						Databus <= reg_ram_s(22);
--					elsif Address = SWITCH_BASE+7 then--x17
--						Databus <= reg_ram_s(23);
--					elsif Address = LEVER_BASE then--x20
--						Databus <= reg_ram_s(32);
--					elsif Address = LEVER_BASE+1 then
--						Databus <= reg_ram_s(33);
--					elsif Address = LEVER_BASE+2 then
--						Databus <= reg_ram_s(34);
--					elsif Address = LEVER_BASE+3 then
--						Databus <= reg_ram_s(35);
--					elsif Address = LEVER_BASE+4 then
--						Databus <= reg_ram_s(36);
--				 	elsif Address = LEVER_BASE+5 then
--						Databus <= reg_ram_s(37);
--				  	elsif Address = LEVER_BASE+6 then
--						Databus <= reg_ram_s(38);
--				  	elsif Address = LEVER_BASE+7 then
--						Databus <= reg_ram_s(39);
--				 	elsif Address = LEVER_BASE+8 then
--						Databus <= reg_ram_s(40);
--					elsif Address = LEVER_BASE+9 then--x29
--						Databus <= reg_ram_s(41);
--					elsif Address = CAL_OP then--x31
--						Databus <= reg_ram_s(49);
--					elsif Address = T_STAT then--x32
--						Databus <= reg_ram_s(50);
--					else
--						Databus <= (others => 'Z');
--					end if;
--			else
--		     Databus <= (others => 'Z');
--			end if;
--		else Databus <= (others => 'Z');
--      end if;
--	end if;
--end process ram;
--
-------switches display-------------------------------
--
--switches(0) <= reg_ram_s(16)(0); --x10 to x17
--switches(1) <= reg_ram_s(17)(0); 
--switches(2) <= reg_ram_s(18)(0); 
--switches(3) <= reg_ram_s(29)(0); 
--switches(4) <= reg_ram_s(20)(0); 
--switches(5) <= reg_ram_s(21)(0); 
--switches(6) <= reg_ram_s(22)(0); 
--switches(7) <= reg_ram_s(23)(0); 
--
-------glow the LED for 7 segment display--------------------------
--with temp_led(7 downto 4) select
--Temp_H <=
--    "0000110" when "0001",  -- 1
--    "1011011" when "0010",  -- 2
--    "1001111" when "0011",  -- 3
--    "1100110" when "0100",  -- 4
--    "1101101" when "0101",  -- 5
--    "1111101" when "0110",  -- 6
--    "0000111" when "0111",  -- 7
--    "1111111" when "1000",  -- 8
--    "1101111" when "1001",  -- 9
--    "1110111" when "1010",  -- A
--    "1111100" when "1011",  -- B
--    "0111001" when "1100",  -- C
--    "1011110" when "1101",  -- D
--    "1111001" when "1110",  -- E
--    "1110001" when "1111",  -- F
--    "0111111" when others;  -- 0
--
--with temp_led(3 downto 0) select 
--Temp_L <=
--    "0000110" when "0001",  -- 1
--    "1011011" when "0010",  -- 2
--    "1001111" when "0011",  -- 3
--    "1100110" when "0100",  -- 4
--    "1101101" when "0101",  -- 5
--    "1111101" when "0110",  -- 6
--    "0000111" when "0111",  -- 7
--    "1111111" when "1000",  -- 8
--    "1101111" when "1001",  -- 9
--    "1110111" when "1010",  -- A
--    "1111100" when "1011",  -- B
--    "0111001" when "1100",  -- C
--    "1011110" when "1101",  -- D
--    "1111001" when "1110",  -- E
--    "1110001" when "1111",  -- F
--    "0111111" when others;  -- 0
--
--end Behav;
--
